C c++ php laravel vuejs reactjs nodejs expressjs python django java Verilog RTL Coding RTL Design System Verilog System Verilog Assertions UVM Perl Cpp Code coverage Functional Code Coverage AXI AHB APB UART I2C FIFO ASIC FPGA HDL/HVL Verification Methodology EDA Tools Verilog System Verilog UVM Methodologies functional Verification Perl AHB APB AXI SPI Mentor Questa Model sim Quartus Prime Linux environment digital electronics Advanced Verilog STA VLSI Design Tcl Physical Design Low power Verification EM-IR Analysis Calibre Synthesis Unix Physical Verification Shell Cmos SOC debugging DDR3 Static Timing Analysis Place & Route Clock Tree Synthesis Physical/Layout Verification Design for Testability Unified Power Format Verilog, TCL and C LINUX FLOORPLANNING CTS COMMUNICATION Logical Synthesis Vim digital logic design vlsi protocols GPIO LPDDR4 jtag verdi regression c, verilog, python, sql, machine learning USB MIPI xilinx VIVADO Degital System Verilog Constraints AMBA AXI AMBA APB UFS(Universal Flash Storage) system verilog assertion RISC-V design and verification Arduino CMOS Digital VLSI sv Analog Layout Design Layout Techniques Semiconductor Technology Design rules & Guidelines Signal Integrity Team collaboration Attention to Detail Powerplan PnR DRC/LVS EMIR LPC Synopsys DC Synopsys ICC II Synopsys LC & LM Synopsys PT Synopsys ICV Synopsys StarRC MS Word MS Excel MS Powerpoint TCL Scripting verification DS ARM RTOS MODBUS CAN IoT Floorplan placement sign-off stage embedded linting Computer Architecture pcie Linux basics Synopsis VCS circuit designer ADIC Low power vlsi design cadence Xilinx PSOC Creator spice operating systems verification using system verilog DFT standard cell layout design Digital circuit Design UVM RAL route engineering change order Digital Design Design Verification basics of TCL logic synthesis place and route VUM injection molding,Assenmbly Machines CDC data structures microcontroller (pic18f4580) Embedded c programming Virtuoso Genus Innovus OpenRoad Matlab LTspice Analog circuit opamp Cadence virtuoso Rtl to Gds Vhdl Constraints QVIP pv icc2 sdhc ATPG MBIST scan insertion OCC Network theory Analog Electronics Block level chip design,using 32nm and 28nm,STA, synthesis, Robotics PCB Layout antenna effect matching latchup drm TSMC nbflow •Hardware Description Languages xillinx communication system electronics devices and circuits control system signal and system gvim routing i3c Floorplan, powerplan, placement, CTS, routing, timing closure, STA FPGA VERIFICATION digit logic Design sv constraints microcontroller computer networking amba ahb DIGITAL, VERILOG,SV,UVM synopsys tool synopsys vsc oops SV Assertions Clock Domain Crossing Regression testing Testbench creation perl basics verilogA digital ic design RF Fusion Compiler advance digital design system architecture c and c++ apnr TCP/IP DRC HR digital marketing HTML Language :Verilog,SV,UVM. Script :Perl,Python. Protocols:APB,AHB,AXI,I2C. Tools :Questasim,gvim,git. Operating Tools:Window/linux. SQL devops aws css git github RTL Verification backend design